1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to transistors having strained channel regions by using embedded semiconductor alloys, such as silicon/germanium, to enhance charge carrier mobility in the channel regions of the transistors.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element for complex circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability.
In addition to the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, requiring the adaptation and possibly the new development of highly complex process techniques, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material, i.e., a (100) surface orientation with the channel length aligned to the <110> direction, increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium material next to the channel region to induce a compressive stress that may result in a corresponding strain. When forming the Si/Ge material, the drain and source regions of the PMOS transistors are selectively recessed to form cavities, while the NMOS transistors are masked, and subsequently the silicon/germanium material is selectively formed in the cavities of the PMOS transistor by epitaxial growth.
Although this technique provides significant advantages in view of performance gain of P-channel transistors and thus of complex CMOS devices, it turns out, however, that a further increase of the strain component in the channel region may be difficult to achieve by further reducing the lateral offset of the silicon/germanium alloy from the channel region without compromising integrity of the gate electrode structure, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a conventional semiconductor device 100 at an early manufacturing stage. The semiconductor device 100 comprises a substrate 101, typically silicon substrates are used, above which may be formed a buried insulating layer (not shown), if a silicon-on-insulator (SOI) architecture is considered. Moreover, a silicon semiconductor layer 102 is formed above the substrate 101 and represents an active semiconductor material for forming therein and thereon circuit elements, such as transistors and the like. The semiconductor layer 102 comprises a plurality of active regions wherein, for convenience, a first active region 102A and a second active region 102B are illustrated in FIG. 1a, which are laterally separated by an isolation structure 103 provided in the form of a shallow trench isolation. The active region 102A is an appropriately doped semiconductor material for forming therein and thereabove a P-channel transistor 150A, while the active region 102B is appropriately configured in order to provide the basic characteristics for an N-channel transistor 150B. As illustrated, each of the transistors 150A, 150B comprises a gate electrode structure 151 including a gate electrode material 151A, a dielectric cap layer 151B formed above the gate electrode material 151A, and a gate insulation layer 151C, which separates the gate electrode material 151A from a channel region 152 in the corresponding active regions 102A, 102B. Furthermore, a spacer element 104A, also referred to as an offset spacer, is formed on sidewalls of the gate electrode structure 151 of the P-channel transistor 150A, possibly in combination with an etch stop liner 105, and the like. The N-channel transistor 150B is covered by a spacer layer 104, possibly in combination with the etch stop liner 105. Furthermore, an etch mask 106 is formed above the active region 102B, for instance in the form of a resist material and the like.
The semiconductor device 100 is typically formed on the basis of the following process techniques. After delineating the active regions 102A, 102B by forming the isolation structure 103 and performing appropriate implantation sequences in order to provide the basic doping in the active regions 102A, 102B, the gate electrode structures 151 are formed by providing an appropriate material for the gate insulation layer 151C followed by the deposition of a gate electrode material 151A and the dielectric cap material 151B. For this purpose, well-established oxidation, surface treatments and deposition techniques may be used, depending on the overall configuration of the gate electrode structures. During the patterning of these material layers, sophisticated lithography techniques and etch processes are used in order to obtain the gate electrode structures 151 with a desired gate length according to device requirements. Next, the etch stop liner 105, if required, may be formed by deposition and/or oxidation, followed by the deposition of the spacer layer 104, which is typically deposited as a silicon nitride material by using thermally activated chemical vapor deposition (CVD) recipes, plasma assisted processes and the like. When depositing the spacer layer 104, a thickness thereof is selected in view of a desired width 104W of the spacer element 104A, which in turn determines an offset of a silicon/germanium alloy to be formed in the active region 102A in a later manufacturing stage. Since the width 104W essentially determines the offset of a silicon/germanium material when applying substantially anisotropic etch recipes during the further processing, the width 104W is typically reduced in order to enhance the strain-inducing effect achieved by the silicon/germanium material. That is, for given deposition recipes and hence material compositions of the silicon/germanium material, the lateral offset of the strain-inducing material from the channel region 152 significantly influences the finally obtained strain and thus performance gain of the transistor 150A, in particular when extremely scaled devices are considered having gate lengths of 50 nm and significantly less. A reduced thickness of the spacer layer 104 may thus be desirable in view of a pronounced performance gain of the transistor 150A. On the other hand, the reduction in thickness is limited in view of preserving the integrity of the gate electrode materials 151A and of the gate insulation layer 151C, if, for instance, comprising very sensitive materials, such as high-k dielectric materials and the like. After forming the spacer layer 104 on the basis of a thickness that is a compromise between performance gain of the transistor 150A and integrity of the gate electrode structure 151, the etch mask 106 is formed on the basis of lithography techniques in order to cover the transistor 150B, i.e., the corresponding portion of the spacer layer 104, thereby selectively exposing the transistor 150A to an etch ambient 107 that is appropriately selected to remove material of the spacer layer 104, thereby forming the spacer element 104A. The etch process 107 is performed on the basis of well-established plasma assisted anisotropic etch techniques, wherein, if required, a control of the etch process may be accomplished on the basis of the etch stop liner 105. Thereafter, exposed portions of the liner 105 are removed and a further etch process or a further etch step of the process 107 is applied on the basis of appropriately selected etch parameters and an etch chemistry for etching into the active region 102A while using the spacer 104A and the isolation structure 103 as stop materials.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, wherein cavities 108 are formed adjacent to the gate electrode structure 151 and the spacer element 104A within the active region 102A, wherein, due to the anisotropic nature of the preceding plasma assisted etch process, substantially vertical sidewalls 108S are obtained. Consequently, a lateral offset of the cavities 108, and thus of any silicon/germanium alloy still to be formed in a later manufacturing stage, from the gate electrode material 151A is substantially determined by the width 104W of the spacer 104A, possibly in combination with a thickness of the etch stop liner 105, if provided. Consequently, any process variation during the formation of the spacer element 104A and during the subsequent etch process for forming the cavities 108 may affect the resulting transistor characteristics, in particular for highly scaled critical dimensions of the transistors 150A, 150B. That is to say, upon further scaling the gate length of the transistors, any process flow variations, which may not proportionally scale down with the device dimensions, may thus provide an over-proportional effect on the finally obtained transistor characteristics.
FIG. 1c schematically illustrates the device 100 during a selective epitaxial growth process 110, during which a silicon/germanium alloy 111 is formed in the cavities 108 (FIG. 1b), wherein process parameters are appropriately selected such that a significant material deposition may occur on exposed crystalline surface areas, while a deposition on dielectric materials is efficiently suppressed. It is well known that the process parameters, such as flow rates, deposition temperature and the like, may be selected such that a significant growth of material may be obtained on the exposed surface areas, which may represent more or less well-defined crystallographic planes due to the crystalline nature of the active regions 102A, 102B. For example, for a standard crystallographic configuration of the semiconductor layer 102, typically the sidewall 108S, when representing a substantially vertical sidewall, may thus represent a (110) crystal plane or any physical equivalent plane, while the bottom 108B may substantially represent a (100) crystal plane. The process parameters of the deposition process 110 may thus be selected such that a comparable deposition rate may be obtained for these crystallographic planes, while, in other crystallographic orientations, a significantly reduced deposition rate may occur, as is well known in the art.
Consequently, for a given germanium concentration, which may typically be restricted to values of 30 atomic percent and less, the spacer element 104A may substantially determine the resulting strain component in the channel region 152, wherein a further reduction of this offset may be difficult to achieve since the spacer 104A also has to preserve integrity of the gate electrode structure 151 during the preceding processing and during the further processing, for instance in view of complex cleaning steps and the like. Consequently, in addition to any process variations, the relative gain achieved by the incorporation of the embedded silicon/germanium material 111 may be increasingly reduced upon further scaling the transistor dimensions, since the width of the spacer element 104A may not be arbitrarily scaled down in a proportional manner.
In some conventional approaches, it has been suggested to introduce an isotropic etch process so as to obtain a certain degree of under-etching when forming the cavities 108, which, however, may also cause significant process variations and may result in reduced gate integrity, in particular at the edges of the gate electrode structure, depending on the lateral etch rate.
FIG. 1d schematically illustrates the semiconductor device 100 according to further conventional approaches in which the cavities 108 may be formed, at least partially, on the basis of a crystallographically anisotropic etch process, which is to be understood as an etch process in which the etch rate is different in different crystallographic orientations of the crystalline substrate material. For example, a plurality of wet etch chemistries are well known that provide a reduced removal rate with respect to the (111) crystal axis in a silicon lattice so that corresponding crystallographic planes may act as etch stop planes. Consequently, upon a crystallographically anisotropic etch chemistry, for instance based on TMAH (tetra methyl ammonium hydroxide), the cavity 108 may be shaped in a highly controllable manner, for instance after performing a first plasma-based anisotropic etch step, since, upon applying the crystallographically anisotropic etch recipe, the lateral etch rate may show a self-limiting behavior as soon as the sidewalls 108S may represent (111) planes. In this manner, a well-controllable lateral under-etching may be achieved without jeopardizing gate integrity. Thereafter, the silicon/germanium material 111 is formed in the cavities 108, as indicated by the dashed lines, on the basis of selective epitaxial growth recipes, as described above.
Generally, the offset of the material 111 from the channel region 152 may be efficiently reduced on the basis of a given width of the spacer element 104A, thereby providing a certain degree of scalability of the strain-inducing mechanism provided by the material 111. On the other hand, upon further device scaling, the non-uniformities and process fluctuations increasingly affect the performance of the device 100, for instance due to a pronounced variability of transistor characteristics and the like. For example, the degree of overgrowth of the material 111 may have an influence on the transistor characteristics since, in a later manufacturing stage, drain and source regions may have to be formed on the basis of implantation processes and metal silicide may have to be formed in the material 111, at least locally. Moreover, in some approaches, the spacers 104A may also be used for the adjustment of further transistor characteristics, such as the offset of drain and source extension regions and the like, thereby requiring further process steps for forming corresponding spacers in the transistor 150B, wherein the different process history of the resulting spacer elements may also have an influence on the further processing and the like. Moreover, a difference in overall surface topography between the transistors 150A, 150B caused by any overgrowth upon forming the silicon/germanium material 111 may increasingly contribute to device non-uniformities, for instance when forming metal silicide regions, forming contact elements which may connect to the active regions 102A, 102B and the like.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.